Senior FPGA Developer (SystemVerilog)

<div class=&quot;content-intro&quot;><p><img src=&quot;https://i.imgur.com/XN94Hg4.png&quot; alt=&quot;&quot; width=&quot;900&quot; style=&quot;max-width: 100%;&quot;></p> <p>&nbsp;</p></div><p><strong><span data-contrast=&quot;none&quot;><span data-ccp-parastyle=&quot;heading 2&quot;>The Role</span></span><span data-ccp-props=&quot;{&quot;134245418&quot;:true,&quot;134245529&quot;:true,&quot;335559738&quot;:160,&quot;335559739&quot;:80}&quot;>&nbsp;</span></strong></p> <p><span data-contrast=&quot;auto&quot;>The Senior FPGA Developer&nbsp;will be a member of the core team building the&nbsp;Quantum Key Distribution&nbsp;system. The focus is end</span><span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>to</span><span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>end RTL ownership on AMD/Xilinx (Artix</span><span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>7,&nbsp;Kintex&nbsp;UltraScale): architect,&nbsp;implement,&nbsp;verify, and close timing on high</span><span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and&nbsp;mentors&nbsp;a junior engineer.</span><span data-ccp-props=&quot;{}&quot;>&nbsp;</span></p> <p><span data-contrast=&quot;auto&quot;>The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring</span><span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>up, and deliver reproducible, versioned bitstreams.</span><span data-ccp-props=&quot;{}&quot;>&nbsp;</span></p> <p><strong><span data-contrast=&quot;none&quot;><span data-ccp-parastyle=&quot;heading 2&quot;>The Responsibilities</span></span><span data-ccp-props=&quot;{&quot;134245418&quot;:true,&quot;134245529&quot;:true,&quot;335559738&quot;:160,&quot;335559739&quot;:80}&quot;>&nbsp;</span></strong></p> <p><span data-contrast=&quot;auto&quot;>The Senior FPGA Developer should expect to work&nbsp;in&nbsp;the following activities.</span><span data-ccp-props=&quot;{}&quot;>&nbsp;</span></p> <ul> <li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;9&quot; data-list-defn-props=&quot;{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}&quot; data-aria-posinset=&quot;1&quot; data-aria-level=&quot;1&quot;><span data-contrast=&quot;auto&quot;>RTL architecture, interfaces, and&nbsp;rather high-speed&nbsp;datapaths</span> <ul> <li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;9&quot; data-list-defn-props=&quot;{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}&quot; data-aria-posinset=&quot;1&quot; data-aria-level=&quot;1&quot;>Owning SystemVerilog RTL architecture/implementation for Artix<span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>7 and&nbsp;Kintex&nbsp;UltraScale&nbsp;(SystemVerilog,&nbsp;Vivado)</span></li> <li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;9&quot; data-list-defn-props=&quot;{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}&quot; data-aria-posinset=&quot;1&quot; data-aria-level=&quot;1&quot;>Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third<span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>party MAC/PCS IP</span></li> <li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;9&quot; data-list-defn-props=&quot;{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}&quot; data-aria-posinset=&quot;1&quot; data-aria-level=&quot;1&quot;>Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low<span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>level protocols&nbsp;—&nbsp;</span> <span data-contrast=&quot;auto&quot;>and bridging them to high</span><span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>throughput interfaces (DDR/PCIe)</span></li> <li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;9&quot; data-list-defn-props=&quot;{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}&quot; data-aria-posinset=&quot;1&quot; data-aria-level=&quot;1&quot;>Defining clear AXI/AXI<span data-contrast=&quot;auto&quot;>‑</span><span data-contrast=&quot;auto&quot;>Stream boundaries and register maps for SW/FW integration</span><span data-ccp-props=&quot;{}&quot;>&nbsp;</span></li> </ul> </li> </ul> <ul> <li data-leveltext=&quot;&quot; data-font=&quot;Symbol&quot; data-listid=&quot;9&quot; data-list-defn-props=&quot;{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469…